Improved the channel assignment mechanism for hardware i/o and instrument side-chains.Fixed a bug causing open effect window positions to migrate down every time the project is saved/reopened.".If you have how to work them in my design, please teach me. In this settings, the controller open SBU only few seconds, before hadn't finished DP AUX negotiation.Īre there no way to work internal MUX at no supporting Thunderbolt? I also tried to change this setting to "Full SBU MUX Configuration" and "SBU MUX without polarity change", but didn't work well. However, I want to work switching SBU regardless Type-C plug direction. I understand this work, because it's "pass-through". In default settings(Thunderbolt Host Configuration -> SBU MUX Configuration -> Pass-through), my design can DP Alt mode in one direction Type-C plug.
In this article, "However, an SBU mux is required if the CCG5 design was targeted at supporting only USB3 and DisplayPort Alt Mode." I interpret this mention as CCG5 needs the external MUX for SBU, if it support only USB3 and DisplayPort Alt Mode. I use CYPD5225-96BZXI (CYPD5225-96BZXI_notebook_tgl_config_3_4_0_2559_0_0_0_nb.xml" in EZ-PD CCGx Host SDK) that targeted at supporting USB3 and Type-C PD, DP Alt Mode.īut my design have not work switching SBU for DP AUX, and I found below article KBA235416. I'm sure more questions will come up as we proceed but these are a few items that are gating our working, we are following the EVK Reference as a starting point, but more guidance would be appreciated. We're essentially looking to have two USB Type-C ports with identical functionality from the user perspective to eliminate any confusion when selecting a port for power input/data output.ġ - Which I2C pins should we use to support field upgrade programming?Ģ - What other pins are required to enable the bootloader for I2C programming?ģ - Can this same I2C interface be used for general register interrogation?Ĥ - Do you have a document that details the Altmode or VDM exchange along with when items like HPD are asserted?ĥ - Could you detail the default configuration of the CCG4? Which PD voltages/currents are supported by default, what is the default behavior of the various GPIO, etc? Ideally the base load would be sufficient for us to get started rather than needing to rewrite all the code, so this will help us determine the scope of work. I've attached a deck that shows the current or default configuration of our USB ports and our future state which involves a lot of muxing in addition to adding the CCG4 to manage the PD/Altmode side of things. With respect to the CCG4, we've got some configuration/IO questions for Infineon to support our implementation.
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